FX365C product information cml semiconductor products publication d/365c/3 october 1995 applications mobile radio systems community base stations sports radio (japan) sub-audio signalling and selec- tive calling status and alarm systems amateur radio features low-voltage (3-volt) supply 39 programmable sub-audio tones + n otone meets mpt1306 and eia - 220 b high v oiceband/ctcss isolation separate sub-audio and rx/tx audio paths and filtering digital period detector output latch xtal/clock generator 8-bit latch tone generator program logic xtal/clock tx enable tx rx tx (rx) control control tone frequency bus (rx) sub-audio tone input rx audio input rx audio output rx tone detect tx tone output tx audio input tx audio output v dd v bias v ss serial enable 1/d 5 serial enable 2/d 4 serial data/d 3 serial clock/d 2 d 1 d 0 ptl decode comparator ref. decode comparator input decode comparator 8-bit serial shift register logic logic 300hz f tone xtal + - rx tone decode output load/latch voice-audio path sub-audio path rx/tx v dd 3 2v dd 3 low-voltage ctcss encoder/ decoder FX365C brief description the FX365C is a 3-volt, half-duplex predictive continuous tone controlled squelch system (ctcss) encoder/decoder microcircuit. the FX365C has integral voice-band filtering for prefiltering of tx audio and the rejection of the ctcss tone in receive. under processor control, the FX365C will encode and decode any one of 39 sub-audio frequencies (+n otone ) in the range 67.0hz to 250.3hz. tone frequencies and all functional commands can be loaded to the device in either pin-selectable 8-bit parallel or serial format. a separate, rx/tx voice-audio path is available with a highpass (sub-audio reject) filter automatically placed in the relevant rx or tx voice line. the rx sub-audio (ctcss) path contains a (selected tone frequency) bandpass filter and period detector providing a logic level output (rx tone detect) to indicate a successful decode operation. rx press to listen (ptl) and tx squelch-tail elimination functions are available in both command loading modes. the squelch-tail elimination function will provide (tx tone) phase-reversal to minimise the annoying audio outputs that occur at the receiver on completion of a transmission. tone frequencies and filter accuracies are maintained by an on-chip 1.0mhz clock oscillator employing an external crystal or clock pulse input. the FX365C, which exhibits high audio and sub- audio performance with low falsing, is available in 24- pin dil and small outline smd packages. fig.1 functional block diagram
2 pin number function dw and j package styles. v dd : positive supply rail. a single stable supply is required; levels and voltages within the FX365C are dependent upon this supply. this pin should be decoupled to v ss by a capacitor located close to the pin. xtal/ciock: input to the on-chip inverter; used with a 1.0mhz xtal or external clock source. xtal: output of the on-chip clock oscillator inverter. load/latch: controls 8 on-chip latches and is used to latch rx/tx, ptl, d 0 - d 5 . this pin is internally pulled to v dd . a logic 1 applied to this input places the 8 latches into a 'transparent' mode. a logic 0 applied to this input places the 8 latches into the latched mode. in parallel mode data is loaded and latched by a logic 1 to 0 transition (see figure 4a). in serial mode data is loaded and latched by a 0 to 1 to 0 strobe pulse on this pin (see figure 4b). d 5 /serial enable 1: data input d 5 (parallel mode); serial enable 1 (serial mode). a logic l applied to this input, together with a logic 0 applied to d 4 /serial enable 2, will put the device into 'serial mode' (see figure 4b). this pin is internally pulled to v dd . d 4 /serial enable 2: data input d 4 (parallel mode); serial enable 2 (serial mode). a logic 0 applied to this input, together with a logic 1 applied to d 5 /serial enable 1, will place the device into serial mode (see figure 4b). this pin internally pulled to v dd . d 3 /serial data: data input d 3 (parallel mode); serial data input (serial mode). in serial mode this pin becomes the serial data input for d 5 - d 0 , rx/tx, ptl (see figure 4b). d 5 is clocked-in first and ptl last. this pin internally pulled to v dd . d 2 /serial clock: data input d 2 (parallel mode); serial clock input (serial mode). in serial mode this pin becomes the serial clock input. data is clocked on the positive-going edge (see figure 4b). this pin is internally pulled to v dd . d 1 : data input d 1 (parallel mode); not used (serial mode). this pin is internally pulled to v dd . d 0 : data input d 0 (parallel mode); not used (serial mode). this pin is internally pulled to v dd . v ss : negative supply (gnd). decode comparator ref. (i/p) : internally biased to v dd /3 or 2v dd /3 via 1.0m w resistors depending on the logical state of the tone decode output pin, this input provides the decode comparator reference voltage; switching of bias voltages provides hysteresis to reduce 'chatter' under marginal conditions. tone decode output = logic 1 will place this input to 2v dd /3 bias, a logic 0 will bias this input to v dd /3. FX365C 1 2 3 4 5 6 7 8 9 10 11 12
3 FX365C 13 14 15 16 17 18 19 20 21 22 23 24 pin number function dw and j package styles. rx tone decoder (o/p) : the gated output of the on-chip decode comparator. this output is used to gate the rx audio path. a logic 0 output on this pin indicates a successful decode and indicates that the decode comparator input pin is more positive than the decode comparator ref input (see table 1). decode comparator input: the inverting input of the decode comparator. this pin is to be connected to the rx tone detect pin via external integrating components as shown in figure 2. rx tone detect (o/p) : in the rx mode this output will go to a logic 1 during a successful decode (table 1). this pin is to be connected to the decode comparator input via the external integrating circuitry as shown in figure 2. tx tone output: a low-impedance emitter-follower source, under the control of the rx/tx pin, of the ctcss sinewave. this output, when not transmitting a sub-audio tone, may be set to a v dd /(2-0.7)v bias or open-circuit as described in table 1. rx/tx: this input (parallel mode) selects rx or tx modes (see figure 2). logic 1 = rx; logic 0 = tx. in serial mode this (rx or tx) function is serially loaded via pin 7 (serial data) and this pin not used. this pin is internally pulled to v dd via a 1m w resistor (rx operaion). ptl: a dual-function input. in the parallel load mode, rx operation: a logic 1 provides a press to listen function by overriding the tone-squelch and enabling the audio path. in the parallel load mode, tx operation: a logic 1 provides a squelch tail elimination function by reversing the phase of the transmitting sub-audio tone; the phase reversal function should be applied by a suitable timing circuit. in the serial load mode (rx and tx) these functions are loaded via the serial data word at pin 7. rx audio output: the high-pass filtered received audio output. this pin outputs audio when rx tone decode = 0, or ptl = 1 or notone is programmed (table 2). in tx mode this pin is biased to v dd /2. tx audio output: the high-pass filtered transmit audio output. in tx mode this pin outputs audio present at the tx audio input by opening the tx audio path. in rx mode this pin is biased to v dd /2. v bias : the output of the on-chip analogue bias circuitry. held internally at v dd /2, this pin should be externally decoupled to v ss . tx audio input: the tx audio input pin. tx voice-band audio may be prefiitered, using the voice audio path, thus helping to avoid talk-off due to the intermodulation of speech frequencies with the transmitted ctcss tone. the tx audio path may also be used to pre-filter speech when employing scramblers which could introduce noise into the low frequency band. this pin is internally biased to v dd /2. rx audio input: the input to the voice audio high-pass filter in the rx mode. this pin is internally biased to v dd /2. tone input: the input to the ctcss tone detector and is internally biased to v dd /2.
4 application information xtal xtal/clock load/latch l/latch sdata sclock parallel load mode serial load mode [differences] tone in FX365C tx audio in tx audio out rx audio out tone out rx tone decode out decode comp in ptl (parallel load) rx/tx (parallel load) rx audio in d 5 d 4 d 3 d 2 d 1 d 0 v bias v dd v dd v dd v ss v ss v ss v ss 1 2 3 11 12 24 23 22 21 20 19 18 18 17 17 16 15 14 13 xtal xtal/clock 2 3 v ss c 1 c 2 x 1 r 1 c 8 c 3 c 5 c 6 c 7 r 2 r 3 d 1 c 4 4 5 6 7 8 9 10 4 5 6 7 8 9 10 x x x x x c 4 0.1f 20% c 5 0.1f 20% c 6 1.0f 20% c 7 0.1f 20% c 8 1.0f 20% d 1 small signal type x 1 1.0mhz external components component value tolerance r 1 1.0m w 10% r 2 820k w 10% r 3 330k w 10% c 1 68.0pf 20% c 2 33pf 20% c 3 0.1f 20% fig.2 recommended external components input pin condition output pin condition result and/or function decode tone tx tone tx audio tone rx audio comp. rx tone rx tone tx phase path decoder path d 0 to d 5 rx/tx ptl input detect decode enabled rev ersed enabled enabled enabled notes t one 00 x 01 y es n o y es n o n o ( bias )1 a t one 01 x 01 y es y es y es n o n o ( bias )1 b n otone 0 xx 01n o ( bias ) x y es n o n o ( bias )2 t one 10 0 0 1 n o ( o / c ) x n o y es y es 3 a t one 11 0 0 1 n o ( o / c ) x n o y es y es 3 b t one 1 x 110n o ( o / c ) x n o y es y es 4 n otone 1 xx x 0n o ( o / c ) x n o y es y es 5 n otes 1 a normal tone transmit condition. 1 b tone tx with phase reversed. 2n otone programmed in tx mode; tone transmit output set to v dd /2 -(0.7v). tx audio path enabled. 3 a normal decode standby. 3 b normal decode standby with ptl used to enable audio. 4 normal decode of correct ctcss tone condition; ptl has no effect. 5n otone programmed in rx mode; tone transmit output (o/c). rx audio path enabled. table 1 combinations of input/output conditions x = don't care
5 application information ...... nominal FX365C freq (hz) freq. (hz) d d d d d fo % d 0 d 1 d 2 d 3 d 4 d 5 67.0 67.05 +0.7 111111 69.3 69.32 +0.03 100111 71.9 71.90 0.0 111110 74.4 74.35 -0.07 011111 77.0 76.96 -0.05 111100 79.7 79.77 +0.09 101111 82.5 82.59 +0.10 011110 85.4 85.38 -0.02 001111 88.5 88.61 +0.13 011100 91.5 91.58 +0.09 110111 94.8 94.76 -0.04 101110 97.4 97.29 -0.11 010111 100.0 99.96 -0.04 101100 103.5 103.43 -0.07 001110 107.2 107.15 -0.05 001100 110.9 110.77 -0.12 110110 114.8 114.64 -0.14 110100 118.8 118.80 0.0 010110 123.0 122.80 -0.17 010100 127.3 127.08 -0.17 100110 131.8 131.67 -0.10 100100 136.5 136.61 +0.08 000110 141.3 141.32 +0.02 000100 146.2 146.37 +0.12 111010 151.4 151.09 -0.20 111000 156.7 156.88 +0.11 011010 162.2 162.31 +0.07 011000 167.9 168.14 +0.14 101010 173.8 173.48 -0.19 101000 179.9 180.15 +0.14 001010 186.2 186.29 +0.05 001000 192.8 192.86 +0.03 110010 203.5 203.65 +0.07 110000 210.7 210.17 -0.25 010010 218.1 218.58 +0.22 010000 225.7 226.12 +0.18 100010 233.6 234.19 +0.25 100000 241.8 241.08 -0.30 000010 250.3 250.28 -0.01 000000 n otone n otone 000011 serial input mode x x clock data 0 1 table 2 tone programming information passband frequency (hz) gain (db) stopband 100 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 300 1000 v dd =3.5v 3000 fig.3 voiceband filter response
6 specification absolute maximum ratings exceeding the maximum rating can result in device damage. operation of the device outside the operating limits is not implied. supply voltage -0.3 to 7.0v input voltage at any pin (ref v ss = 0v) -0.3 to (v dd + 0.3v) sink/source current (supply pins) +/- 30ma (other pins) +/- 20ma total device dissipation @ t amb 25c 800mw max. derating 10mw/c operating temperature range: FX365C j -40c to +85c (cerdip) FX365C dw -40c to +85c (plastic) storage temperature range: FX365C j -55c to +125c (cerdip) FX365C dw -40c to +85c (plastic) operating limits all device characteristics are measured under the following conditions unless otherwise specified: v dd = 3.3v. t amb = 25c. xtal/clock f 0 = 1.0mhz. signal 0db ref: = 180mvrms. composite signal = 1.0khz audio tone at 0db, noise at C12.0db (gaussian white noise, band-limited to 6.0khz), programmed ctcss tone at -20db. characteristics see note min. typ. max. unit static characteristics supply voltage (v dd ) 3.0 3.3 5.5 v supply current (tx) - 1.5 - ma (rx) - 1.5 - ma sub-audio tone input impedance - 1.0 - m w tx tone output impedance - 4.0 - k w voice-audio input impedance - 1.0 - m w voice-audio output impedance - 1.0 - k w digital input impedance 1 - 1.0 - m w input logic 1 1 70.0 - - %v dd input logic 0 1 - - 30.0 %v dd output logic 1, source = 0.1ma 2 80.0 - - %v dd output logic 0, sink = 0.1 ma 2 - - 20.0 %v dd dynamic characteristics tone decoder decode input signal level 3 -20.0 - - db decode response time 3, 6 - - 250 ms de-response time 3, 6 - - 250 ms decode selectivity 3 0.5 - 3.0 %f o tone encoder tx tone output level - 627 - mvrms tx tone frequency accuracy (f o error) -0.3 - +0.3 %f o risetime to 90% (nominal output) f o > 100hz 4 - 55.0 - ms f o < 100hz 4 - 70.0 - ms tone output load current - - 5.0 ma total harmonic distortion - 2.0 5.0 % output level variation between tones - 0.1 - db spurious emissions - - -48.0 db voice-audio filter and path passband frequencies 300 3000 hz passband gain at 1.0khz - 0 - db w.r.t. 1.0khz -2.0 - 0.5 db total harmonic distortion 5 - 2.0 5.0 % stopband frequencies - - 250 hz stopband attenuation 33.0 36.0 - db output noise level (input a.c. short cct) 7 - -54.0 -48.0 db sinad 8 36.0 40.0 - db audio switch isolation 5 - 60.0 - db
7 (a) parallel mode timing (b) serial mode timing d 0 to d 5 , rx/tx and ptl serial enable function serial data serial clock load data latch data data latched data d 5 data d 4 d 3 rx/tx (rx) ptl or (tx) phase reverse d 5 d 4 d 3 d 2 d 1 and d 0 for wired, non- m p applications, load/latch should be connected to v dd . data load sequence: d5, d4, d3, d2, d1, d0, rx/tx and ptl/phase reverse t l t sp t 1 t ss t c t l t 2 t w load/latch load/latch not used 1.0m w internal pullup characteristics see note min. typ. max. unit specification ...... serial/parallel inputs parallel set-up time (t sp ) 400 - - ns load/latch pulse width (t l ) 400 - - ns serial clock pulse width (t c ) 400 - - ns serial set-up time (t ss ) 400 - - ns serial enable time (t 1 ) 400 - - ns serial load/latch set-up time (t 2 ) 400 - - ns serial clock frequency - 1.0 - mhz notes 1. refers to rx/tx, ptl, decode comparator input, d 0 , d 1 , d 2 , d 3 , d 4 , d 5 inputs. 2. all logic outputs. 3. composite signal test condition. 4. any programme tone and rl = 600 w . cl = 15pf. includes response to a phase-reversal instruction. 5. 1khz reference = 0db. 6. f o > 100hz, (for 100hz >f o >67hz: t = (100/f o hz) x 250ms). 7. measured in a 30khz bandwidth. 8. for an input level of 180mvrms at 1.0khz, in a 30khz measurement bandwidth. fig.4 serial and parallel timing diagrams
package outlines the FX365C is available in the package styles outlined below. mechanical package diagrams and specifications are detailed in section 10 of this document. pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. handling precautions the FX365C is a cmos lsi circuit which includes input protection. however precautions should be taken to prevent static discharges which may cause damage. cml does not assume any responsibility for the use of any circuitry described. no circuit patent licences are implied and cml reserves the right at any time without notice to change the said circuitry. not to scale max. body length 15.57mm max. body width 7.59mm not to scale max. body length 32.00mm max. body width 13.36mm ordering information FX365C dw 24-pin plastic s.o.i.c. (d2) FX365C j 24-pin cerdip dil (j4) FX365C dw 24-pin plastic s.o.i.c (d2) FX365C j 24-pin cerdip dil (j4)
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